Staff Analog Mixed-Signal Circuit Design Engineer

Position Summary

We are seeking an experienced Staff Analog Mixed-Signal Circuit Design Engineer to lead the design and implementation of advanced CMOS PLL architectures. This role involves end-to-end responsibility from system-level specifications through layout and testing, focusing on achieving industry-leading jitter, noise, and spur performance.

Key Responsibilities

• Define advanced CMOS Phase Locked Loop (PLL) architectures and conduct device-level design and verification.
• Manage the full design cycle from system specification to production.
• Lead layout planning and execution, ensuring optimal noise reduction and physical implementation techniques.
• Target best-in-class performance in jitter, noise, and spur metrics.
• Architect system designs, choosing optimal configurations (integer, fractional, SS, MDLL, etc.) based on noise, jitter, and spur requirements.
• Determine system parameters such as loop bandwidth, noise margin, noise transfer function, and spur reduction through comprehensive system verification including behavioral and transistor-level modeling using Verilog-A, MATLAB, and SpectreRF.
• Design and validate critical circuit components including LC VCO, R-VCO, MMD, PFD, CP, LF, fractional-N Sigma-Delta Modulator, calibration engine, and Low Dropout Regulators.
• Optimize noise performance targeting sub-100 femtoseconds RMS jitter, wide tuning range extending into multi-Gigahertz frequencies, low power consumption, and robust operation under process, voltage, and temperature variations.
• Develop calibration logic such as ADC-based VCO gain tracking, background spur reduction, and DTC linearization.
• Oversee layout floor planning emphasizing noise minimization techniques such as guardring, shielding, and isolation practices alongside EMIR considerations.
• Conduct chip verification and tuning with automation tools including LabVIEW and Python, using instrumentation such as oscilloscopes, spectrum analyzers, signal sources, and phase noise analyzers.
• Produce comprehensive design documentation including specifications, test plans, result reports, and application notes.
• Create reusable PLL IP packages encompassing behavioral models, process design kits (PDK), and testing platforms.

Required Qualifications

• Bachelor, Master, or PhD degree in Electronic Engineering, Microelectronics, or related disciplines.
• Over 8 years of relevant professional experience within the semiconductor industry, particularly in custom or RF design flows.
• Expertise with RF and mixed-signal laboratory instruments such as high-bandwidth oscilloscopes, signal generators, vector network analyzers, spectrum analyzers, phase noise testers, and probe stations.
• In-depth knowledge of phase noise, jitter phenomena, VCO push-pull effects, power supply sensitivity, local oscillator leakage, and spur generation mechanisms.
• Proficiency in scripting languages and tools like Python, MATLAB, and Cadence SKILL for data analysis and test automation.
• Strong verbal and written communication skills with experience mentoring junior engineers.