- 경험
- 8세 이상
- 샐러리
- INR 4,000,000 – INR 5,500,000 / year
- 채용 공고
- 1
- 게시됨
- 5시간전
- 작업 모드
- 사무실에서
- 교육
- Not Required
- 적임
- Individuals without formal graduation are eligible to apply.
- 재개하다
- 신청 시 필수 사항
당신이 일하게 될 곳
직무 설명
About the Role
This leadership role focuses on digital design within ASIC engineering, including FSM, CPU sub-systems, complex SoCs, and FPGA validation. As a senior individual contributor, you will collaborate with multidisciplinary teams comprising digital design, analog/mixed-signal, verification, DFT, physical design, firmware, FPGA, CAD, packaging, and post-silicon validation experts.
Responsibilities
- Define digital architecture, interface requirements, design approach, and methodology during concept stages.
- Take ownership of block-level and top-level design alongside block-level verification throughout project execution.
- Support integration of high-speed IP blocks such as ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control logic.
- Collaborate closely with verification teams to ensure thorough functional completeness.
- Work with physical design teams to facilitate readiness for implementation.
- Assist post-silicon teams to ensure effective product bring-up and production release.
Candidate Profile and Requirements
- Bachelor’s or master’s degree in electrical or electronics engineering or related disciplines, with a preference for master’s degrees.
- More than 8 years of practical industry experience in digital design, particularly FSM, CPU subsystems, complex SoCs, and FPGA validation.
- Familiarity with interface protocols like SPI, I2C, APB, AXI, as well as high-speed SerDes, Ethernet, D2D PHY IP, and associated protocols.
- Comprehensive understanding of ASIC/SoC design cycles including RTL development using SystemVerilog, simulation, linting, clock domain crossing (CDC) and reset domain crossing (RDC) checks, synthesis, formal equivalence verification, design for test (DFT), and implementation handoff.
- Good command over full front-end digital design and exposure to a broad range of backend tools such as CDC analysis, synthesis, latch equivalence checking (LEC), and DFT.
- Strong collaboration, communication, and organizational capabilities in addition to excellent analytical, problem-solving, and debugging proficiency.
Additional Information
Location: Pune, India
Salary range: 4,000,000 to 5,500,000 INR annually
Eligibility
No formal graduation requirement is mandatory to apply.