Verification Engineer

Position Overview

This role is for a Design Verification Engineer with at least 4 years of experience. The position focuses on ASIC verification work and requires hands-on exposure to verification methodologies, simulation debug, and end-to-end SoC verification execution.

Core Requirements

The engineer should be comfortable with ASIC design flow and verification best practices. Strong experience in SystemVerilog and UVM is expected, along with working knowledge of at least one widely used industry protocol such as Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR, or an equivalent standard.

Candidates must have delivered at least two SoC verification projects and should also bring experience in one or more of the following areas: UVM, formal verification, mixed-signal simulation, or power-aware simulation.

Technical Responsibilities

The work includes building verification environments, creating regression infrastructure, translating functional needs into verification plans, and performing debugging for both functional and gate-level simulations. The role also involves coverage analysis and driving closure.

Additional Information

This opportunity is based in Nzalae/ Nzawa locations, Kitui County, Kenya and is a full-time onsite position.

For consideration, candidates may share their details at medha.gaur@einfochips.com.