Senior Staff Physical Design Engineer

About the company

EnCharge AI builds advanced AI hardware and software platforms for edge-to-cloud computing. Its in-memory computing approach is designed to deliver much higher compute efficiency and density than leading alternatives, while supporting compact and energy-conscious AI applications. Founded in 2022, the company is guided by seasoned experts from semiconductor design and AI systems.

Role overview

This position is for an experienced Senior Staff Physical Design Engineer who can lead chip-level implementation work using EDA tools. The role centers on physical design, timing closure, and low-power implementation, with a strong emphasis on hands-on Cadence flow experience.

Key responsibilities

• Carry out chip implementation work across top-level and block-level physical design.
• Drive timing closure efforts and resolve related design issues.
• Work extensively with Cadence EDA tools as part of the implementation flow.
• Apply low-power design practices and debug power-related issues.
• Perform EM/IR analysis, power grid checks, and issue resolution.
• Use TCL or Python scripting to automate tasks and improve flow efficiency.
• Support physical verification tasks during routing with an understanding of process concepts.
• Contribute to physical design methodology and evaluate advanced implementation flows.
• Assist with hierarchy-based floorplanning where needed.
• Participate in PDK-related activities and foundry tapeout support as an added advantage.

Qualifications

The ideal candidate should have 10 to 14 years of experience specifically in physical design. Backgrounds focused on logic design or CAD are not counted toward this requirement. Strong knowledge of chip implementation EDA flows is essential, along with practical experience in Cadence tools. A solid understanding of timing concepts, timing closure methods, and low-power design is expected. Experience with both top-level and block-level implementation is required, and hierarchical floorplanning is considered a plus. The role also calls for strong debugging skills in EM/IR and power-grid validation, plus scripting ability in TCL or Python. Familiarity with physical verification, routing-related process concepts, PDK management, and foundry tapeout activities will strengthen the profile.

Eligibility

Candidates with a B.Tech or B.E. degree in Electronics and Telecommunication Engineering, Computer Science and Engineering, Electronics and Communication Engineering, Electrical and Electronics Engineering, Electronics and Computer Engineering, Electronics and Instrumentation Engineering, Electronics, Electrical, or Applied Electronics and Instrumentation may apply.

Work location

The role is based in the Greater Bengaluru Area and follows a hybrid schedule of 2 days in office and 3 days working from home.

Contact

For queries, contact Uday at muday_bhaskar@yahoo.com through Mulya Technologies.