System Verification Engineer

About the Role

The Microcontroller Sub-System IP team delivers critical embedded processing solutions across various domains including IoT, Mobile, Automotive, XR, and Compute. The team focuses on system-on-chip functionalities such as security and power management, supporting multiple business units.

Key Responsibilities

• Contribute to technological innovations and support the team's growth in delivering advanced microcontroller verification solutions.
• Implement cutting-edge verification methodologies including Universal Verification Methodology (UVM) and Formal Verification techniques.
• Design and develop verification assets like testbenches, Universal Verification Components (UVCs), C models, and reusable verification environments with vertical and horizontal structuring.
• Perform coverage analysis to ensure thorough verification and collaborate with design teams to resolve coverage deficiencies.
• Work cross-functionally with design, system-on-chip, and validation teams to address and troubleshoot issues at multiple layers.
• Support integration of microcontroller designs into higher-level system modules, including planning, delivering, and debugging test vectors.

Requirements

• Possess a positive attitude and enthusiasm for inclusive problem-solving.
• Hold a Bachelor's degree in Science, Engineering, or a related discipline.
• Bring over three years of ASIC design verification experience, ideally involving UVM-based methodologies.
• Experience with ISA verification, particularly ARM or RISC-V instruction sets.
• Familiarity with formal verification tools such as Jasper or VC_Formal is advantageous.
• Knowledge of microcontroller or processor subsystem architectures.
• Understanding of AMBA bus protocols.
• Exposure to gate-level simulation debugging and power extraction tools.
• Experience with power-aware verification approaches.
• Skillful in constrained-random and coverage-driven verification methodologies.
• Proficient with System Verilog assertions.
• Strong debugging capability for analyzing test failures and reporting coverage results.
• Extensive hands-on use of RTL simulation tools.
• Programming skills in UVM, System Verilog, Perl, and Python shell scripting.
• Basic knowledge of C and C++ programming languages.