C
AI Chip Architecture Engineer – Hardware/Software Co-Design
Singapore · Tempo pieno
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- Esperienza
- Qualsiasi
- Stipendio
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- Aperture
- 1
- Pubblicato
- 1 settimana fa
- Modalità di lavoro
- In ufficio
- Istruzione
- Bachelor’s degree or above
- Requisiti di ammissibilità
- Bachelor’s degree holders or above in Computer Engineering, Computer Science, Electrical Engineering, or related fields; fresh graduates with strong fundamentals and relevant project experience are encouraged to apply.
- Riprendere
- È necessario candidarsi
Dove lavorerai
Descrizione del lavoro
Role Overview
This position focuses on shaping the architecture of upcoming AI inference chips, with an emphasis on hardware/software co-design for large language model (LLM) workloads. The role sits at the intersection of architecture, compiler flow, and silicon implementation, and is intended for candidates who can translate model requirements into practical chip-level solutions.
Key Responsibilities
- Define and assess architectural capabilities for future-generation AI inference processors.
- Study Transformer and LLM workloads to pinpoint constraints related to performance, power, silicon area, memory usage, and end-to-end latency.
- Investigate accelerator architectures and microarchitectures, covering compute arrays, memory subsystems, network-on-chip design, DMA, scheduling, and data movement patterns.
- Contribute to hardware/software co-design for LLM inference, including operator placement, tiling strategies, memory allocation planning, and compiler-assisted optimization.
- Partner with algorithm, compiler, RTL, verification, and software teams to turn architecture concepts into feasible implementation plans.
- Develop new architectural ideas and support patent creation and technical writing.
Candidate Profile
- A bachelor’s degree or higher in Computer Engineering, Computer Science, Electrical Engineering, or a closely related discipline.
- Solid understanding of computer architecture, AI accelerators, memory organization, interconnects, and performance evaluation methods.
- Working knowledge of Transformer and LLM internals, including attention, FFN, quantization, KV cache, prefill, and decoding.
- Prior exposure to compiler stacks such as MLIR, LLVM, TVM, XLA, or Triton, or experience with kernel-level optimization, is preferred.
- Knowledge of hardware description languages such as Verilog, SystemVerilog, VHDL, or Chisel is an added advantage.
- Strong analytical ability, communication skills, teamwork, and willingness to learn.
- Recent graduates with strong fundamentals and relevant project work are welcome to apply.
Additional Information
This role is based in Singapore and is a full-time onsite position.
No stipend or salary amount was specified in the source details.