Senior Staff Engineer / Technical Lead - Design for Test (DFT)

About Cyient Semiconductor

Join Cyient Semiconductor, an innovator dedicated to developing next-generation System on Chips (SoCs) fueling advancements in AI, automotive, networking, data center, consumer electronics, and industrial fields.

Role Overview

We seek a seasoned Senior Staff Engineer or Technical Lead specializing in Design for Test (DFT) to oversee comprehensive DFT architecture, execution, and sign-off for sophisticated SoC projects across advanced semiconductor technology nodes. This role is based in Bangalore or Hyderabad and requires 6 to 15 years of relevant experience.

Key Responsibilities

• Lead the full lifecycle of DFT implementation covering complex SoCs and intellectual properties (IPs).
• Define and spearhead the DFT architectural framework, test strategies, and testability requirements.
• Take ownership of Scan insertion, Automatic Test Pattern Generation (ATPG), Scan Compression, Memory Built-In Self Test (MBIST), Logic BIST (LBIST), Boundary Scan (JTAG), and fault diagnosis processes.
• Collaborate efficiently with cross-functional teams including Design, Physical Design, Static Timing Analysis (STA), Verification, and Silicon Validation.
• Manage DFT planning from Register Transfer Level (RTL) to silicon bring-up and full-scale production ramp-up.
• Develop, assess, and refine DFT specifications, implementation protocols, and final sign-off methodologies.
• Ensure quality metrics like fault coverage, optimized test pattern counts, and minimized test times are achieved.
• Troubleshoot DFT-related challenges during implementation, verification, and manufacturing phases.
• Engage with clients and stakeholders through technical reviews and project management.
• Provide mentorship and technical guidance to junior engineers and lead the DFT teams.

Technical Proficiencies

• Extensive experience in Scan Architecture, Scan Insertion, ATPG, Scan Compression, MBIST, LBIST, JTAG/Boundary Scan.
• Knowledge of Memory Repair and Redundancy Analysis, Fault Simulation, Silicon Debug, and Failure Analysis.
• Hands-on with prominent DFT tools such as Siemens Tessent Suite (Scan, ATPG, MBIST, Diagnosis), Synopsys DFT Compiler and TestMAX tools, and Cadence Modus DFT Solution.
• Sound understanding of SoC architecture and RTL design principles.
• Proficiency in Verilog/SystemVerilog with insight into low-power DFT strategies.
• Awareness of STA, Timing Closure, Physical Design constraints relevant to DFT.
• Experience with advanced process nodes including 16nm, 7nm, 5nm, and 3nm FinFET technologies.
• Familiarity with IEEE standards such as JTAG, IJTAG, and IEEE 1500.
• Experience working collaboratively with global clients and distributed teams.

Preferred Qualifications

• Educational background: B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, Microelectronics, Electrical Engineering, or related disciplines.
• Demonstrated leadership with a proven track record in leading successful SoC tape-outs.
• Exceptional problem-solving aptitude, leadership capability, and stakeholder communication skills.

Why Join Cyient Semiconductor?

• Work on cutting-edge semiconductor designs and advance technology nodes.
• Lead impactful DFT projects catering to global markets and clients.
• Engage in a collaborative culture fostering strong career progression.
• Gain exposure to next-generation AI, automotive, networking, and high-performance computing designs.