Principal Analog Layout Engineer

About Ciena

Ciena is a global leader in high-speed connectivity dedicated to fostering a people-first culture emphasizing flexibility, growth, well-being, and inclusion. Our innovations in telecommunications technology are paired with a strong commitment to social and community impact.

Role Overview

As a Principal Analog Layout Engineer, you will join the experienced Wavelogic team that has contributed over 30 years of advancements to high-speed broadband fiber-optic modem technologies. This role focuses on crafting top-tier analog layouts for cutting-edge high-speed analog circuits utilizing deep-submicron CMOS and/or BiCMOS technologies. You'll be responsible for analog macros such as DAC and ADC based SERDES solutions for 112G and 224G, optical-line-facing DAC/ADC circuits linked to optical modulators and detectors, transimpedance amplifiers, modulator drivers, and precision analog circuits vital to control and monitoring.

Key Responsibilities

• Design and develop block and macro layout levels including floor-planning, placement, routing, and optimization.
• Perform layout feasibility analyses alongside senior designers to identify optimal circuit layout solutions considering various trade-offs.
• Create and implement automation scripts to enhance layout workflows, including pcell generation.
• Conduct thorough verification via DRC, ANT, LVS, PERC, EM, and IR checks to ensure layouts meet the highest quality standards.
• Troubleshoot and resolve ESD violations identified by PERC tooling.
• Explore and integrate new features in layout tools and processes to improve productivity.
• Provide mentorship to junior layout engineers supporting overall layout efforts.
• Deliver regular progress updates, partake in team discussions, and contribute to knowledge sharing within the group.

Required Qualifications and Skills

• Bachelor’s degree or higher in Electrical Engineering or related field with over 5 years’ relevant industry experience.
• Expertise in custom analog and mixed-signal layout design with in-depth knowledge of deep sub-micron CMOS technologies such as FinFETs.
• Proven experience designing Analog/Mixed Signal layouts including ADC, DAC, PLL, and SERDES components.
• Proficiency with industry-standard EDA tools like Cadence Virtuoso, Siemens Calibre, and Ansys Totem.
• Strong skills in floor planning, device matching, minimizing parasitic effects, RF shielding, electromigration (EM), IR drop, ESD protection, and high-frequency routing techniques.
• Thorough understanding of semiconductor manufacturing processes, foundry technologies, and advanced process effects (LOD, OSE, WPE).
• Ability to analyze and interpret DRC, PERC, ANT, PAD, ERC, and LVS reports effectively.
• Ability to collaborate closely with circuit designers to preemptively identify and resolve layout-related failures.
• Strong analytical, problem solving, and communication skills combined with a proactive, team-oriented mindset.
• Familiarity with scripting languages such as PERL or SKILL is advantageous but not mandatory.
• Track record of successful analog circuit product development and delivery.

Working Environment and Benefits

This role is located onsite in Ottawa, Ontario. Ciena offers a competitive salary ranging between 138000 and 220400 CAD annually, reflecting individual skills, experience, and market factors. Employees may be eligible for discretionary bonuses along with comprehensive benefits, including medical, dental, vision coverage, company-matched retirement programs (DCPP in Canada), Employee Stock Purchase Program, paid holidays, sick leave, vacation time, and adherence to paid family leave policies.

Equal Opportunity Commitment

Ciena fosters an inclusive workplace where all employees are respected and valued, actively opposing discrimination based on disability, veteran status, or other protected categories. Accommodation requests related to hiring are welcomed and supported.