Technical Lead - FPGA Design (Ethernet, PCIe, System Verilog, Xilinx)

About Cisco

Cisco is a global leader in networking, revolutionizing the way people connect and communicate. Established in 1984 by Stanford University computer scientists, Cisco has been at the forefront of Internet Protocol (IP)-based networking advancements. Its innovation spans core routing and switching, Unified Communications, Network Security, Video, Virtualization, and Cloud Computing.

In India, Cisco operates major sales and marketing offices across several cities with a significant R&D presence in Bangalore, which is the largest development center outside the US. Cisco continues to lead the networking technology market including WLAN and security. Cisco India has a workforce exceeding 7,600 employees across R&D, sales, and business support.

Role Overview

This role demands a seasoned FPGA Design Technical Leader with over 12 years of experience, specializing in Ethernet, PCIe, System Verilog, and FPGA development utilizing Xilinx tools.

Key Responsibilities

• Lead the design and implementation of FPGA architectures and solutions.
• Engage in defining the architecture and driving both implementation and verification phases.
• Prepare detailed design specifications and thorough test plans.
• Develop RTL at the block level, execute synthesis, and ensure timing closure.
• Collaborate with cross-functional groups including hardware, software, diagnostics, and signal integrity teams.
• Support complex subsystem lab bring-ups, integration, and validate unit testing.
• Drive adoption and continuous improvement of design processes within the team.
• Provide leadership and mentorship to junior engineers, guiding technical aspects and project success.
• Encourage and facilitate knowledge sharing through sessions such as brown bag talks and design demos.

Candidate Requirements

• Minimum 12 years of experience in FPGA design.
• B.Tech or M.Tech degree in Electrical Engineering or Electronics and Communication.
• Proficient with FPGA platforms such as Xilinx, Altera, and Microsemi.
• Strong competence in HDL languages including Verilog, VHDL, and System Verilog.
• Hands-on experience with FPGA vendor tools like Vivado, Quartus, and Libero.
• Practical knowledge of Ethernet protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, and UART.
• Familiarity with simulation methodologies such as UVM and VMM is advantageous.
• Basic familiarity with Unix systems and scripting tools.
• Ability to champion continuous improvements in design methodologies.
• Effective communication skills in English, self-driven attitude, and strong interpersonal abilities.

Preferred Qualifications

• Understanding of signal integrity concepts and system bring-up procedures.