DFT Design Engineer

About the Company

7Rays Semiconductors is a forward-looking silicon design organization built by experienced semiconductor leaders, including former CEOs, entrepreneurs, and senior industry experts. The company focuses on delivering advanced ASIC solutions across the full development cycle, from early specifications through postsilicon support. Its work spans multiple turnkey and ODC projects, with an emphasis on improving silicon performance, area, and power while raising the bar for engineering quality and service.

Role Overview

The DFT Design Engineer will work on design-for-test implementation and verification for complex semiconductor projects. This position requires strong practical exposure to scan and memory test methodologies, simulation-based validation, and debugging across multiple tools and teams. The role also involves coordination with STA, physical design, customer teams, and internal engineering groups, along with mentoring responsibilities.

Key Responsibilities

• Apply a solid understanding of BSCAN, MBIST, scan, ATPG, and simulation flows.
• Perform MBIST insertion, scan insertion, ATPG pattern generation, and related simulation checks using Cadence, Siemens Tessent, or Synopsys tools.
• Validate MBIST and BSCAN flows through functional and timing simulations.
• Work on both zero-delay and SDF-based timing simulations.
• Debug issues effectively in GUI-based simulators such as VCS, NCSim, or Xcelium.
• Handle fault models including stuck-at, transition delay faults, and IDDQ, and contribute to scan coverage improvement.
• Support SoC-level DFT work, including OCC/OPCG insertion, EDT/compression logic, and scan clock module handling.
• Contribute to post-silicon bring-up and/or production support, including tester debugging through shmoo plots and related analysis.
• Provide test-mode timing constraints to STA and physical design teams.
• Collaborate with cross-functional internal teams and customer teams, while also contributing to guidance and mentoring within the DFT group.

Required Skills and Experience

• Hands-on experience with MBIST insertion and memory test flows.
• Practical knowledge of scan insertion and ATPG pattern development.
• Experience with DFT simulation and debug in industry-standard environments.
• Exposure to fault models such as stuck-at, TDF, and IDDQ.
• Understanding of SoC-level DFT integration and compression-based test solutions.
• Ability to work with test-mode constraints for STA and PD teams.
• Strong debugging ability and familiarity with simulator GUI workflows.
• Good communication skills for working with internal teams and external stakeholders.
• Perl or Tcl scripting knowledge will be an added advantage.

Eligibility

Applicants should hold a B.Tech or B.E. degree in one of the following: Electronics and Telecommunication Engineering, Electronics and Communication Engineering (ECE), Electrical and Electronics Engineering (EEE), Electronics and Computer Engineering, Electronics and Instrumentation Engineering, or Electronics.

Additional Information

This role is based in Bengaluru, India. The position requires close collaboration with multiple engineering teams and customer teams, and the selected candidate is expected to bring both technical depth and mentoring capability.